The present invention relates to a power voltage regulator circuit for lowering a power voltage, which is supplied from the outside, as an internal power source within a semiconductor integrated circuit (IC) device.
The integration density of a semiconductor IC device has recently been increased with rapidity. For example, in a large-scale integrated (LSI) memory device, MOS transistors having a gate length of a submicron order are employed to form a memory unit. Submicron MOS transistors are prone to be adversely affected in a high electric field, and, therefore, they need to be operated with a power voltage lower than 5 V, which is generally employed in a computer system. A power voltage regulator circuit is formed within a single semiconductor chip along with a memory unit, in order to provide a power voltage of a predetermined level.
FIG. 1 shows conventional power voltage regulator circuit 10. Load circuit 12 is an integrated circuit, for example, a memory unit, and is operated with internal power voltage VI produced from regulator circuit 10. Regulator circuit 10 includes P-channel MOS transistor 14, which serves as a variable resistor, and differential amplifier 16 for controlling a gate voltage of MOS transistor 14. The source of MOS transistor 14 is connected to power terminal VDD to which an external power voltage is supplied. The drain of MOS transistor 14 serves as an output terminal of regulator circuit 10, from which internal power voltage VI is produced. Load circuit 12 is connected between the drain of MOS transistor 14 and power terminal VSS set to the ground potential. The source of MOS transistor 14 is electrically connected to a back gate, that is, a semiconductor region having a surface area which serves as a channel of MOS transistor 14, so that the semiconductor region is set to a potential equal to that of power terminal VDD.
Differential amplifier 16 comprises N-channel MOS transistors 18 and 20 constituting a differential pair, N-channel MOS transistor 22 serving as a constant voltage source, and P-channel MOS transistors 24 and 26 constituting a current mirror load. Resistor elements R1 and R2 are connected in series between power terminals VDD and VSS, thereby to form a voltage divider that generates reference voltage VR. Reference voltage VR is supplied to the gate of MOS transistor 18, and an output voltage of regulator circuit 10, or internal power voltage VI, is fed to the gate of MOS transistor 20. When a current flows through load circuit 12, a voltage drop occurs in MOS transistor 14, and internal power voltage VI is made lower than the external power voltage. Differential amplifier 16 compares internal power voltage VI and reference voltage VR, and controls the gate of MOS transistor 14 so as to reduce the difference between voltages VI and VR.
Regulator circuit 10 is, however, not suitable for an LSI device of the type which is required to be operated with a small power consumption. In the design of a static-type random access memory (SRAM), there is a case in which the power consumption is limited to 50 mA or less. Differential amplifier 16 of a current-mirror type consumes relatively large amount of current, that is, about 5-6 mA. Therefore, it is difficult to satisfy the requirement of the power consumption, without degrading the characteristics of the SRAM.